An array substrate is provided with structures such as gate lines, data lines, thin film transistors and pixel electrodes, and the above-mentioned structures are made of conductive materials of different layers. Typically, the array substrate is of a layered structure and comprises a gate metal layer forming gate electrodes, a source-drain metal layer forming source electrodes and drain electrodes of the thin film transistors and a pixel electrode layer forming the pixel electrodes. Some array substrates are further provided with a common electrode layer forming a common electrode. A gate line is connected with a gate electrode of a thin film transistor; a data line is connected with a source electrode of the thin film transistor; and the gate line is used for turning on the thin film transistor, and the data line is used for inputting a voltage signal to a pixel electrode through the thin film transistor. A wiring region (or referred to as a sector) is disposed in a non-display region on the edge of the array substrate to implement a connection between signal lines and a drive circuit; each of the signal lines includes a portion distributed in a display region of the array substrate, and a portion distributed in the non-display region of the array substrate; and generally, a plurality of signal lines is provided within the wiring region.
When the signal lines are gathered in the wiring region, there may be different distances of paths traversed by the signal lines. The different paths traversed by the signal lines, in a case where a conductive material and a width of the signal lines are same, may cause a length difference between the signal lines, which can result in a resistance difference between the signal lines. Thereby, the lengths of the signal lines affect the lengths of the paths for electrical signal transmission, thus result in various lengths of conductive paths, differences in resistance and capacitance, and finally different delays generated in the signal transmission process, and then a display defect is caused.
To solve the above-described problems, a current practice is that a signal line within the wiring region forms a conductive path in a manner of a fold line, so as to extend the length thereof, and to form a length similar to that of other signal lines, so as to ensure that the resistance differences between the signal lines is in a predetermined range, and ensure that the respective signal lines have the same delays for transmitting signals. As shown in FIG. 1, a region surrounded by a broken line in the drawing is a wiring region, i.e., a wiring region S-S′; and the wiring region S-S′ is provided with a signal line 011 close to an edge of the wiring region S-S′, and a signal line 012 located in a centre of the wiring region S-S′. In order that the signal line 011 and the signal line 012 form conductive paths with equal resistance, the signal line 012 is made into a fold line, which result in a larger width of the signal line 012 in the wiring region, instead, and the width of the signal line 012 in FIG. 1 is d. Therefore, the number of the signal lines that the wiring region with the same area can accommodate is reduced, which further results in an increased number of drivers (COF, etc.), and the increased number of drivers can inevitably conducting wire to an increase of drive ICs, and ultimately result in increased costs.